transcript on
if ![file isdirectory verilog_libs] {
	file mkdir verilog_libs
}

vlib verilog_libs/altera_ver
vmap altera_ver ./verilog_libs/altera_ver
vlog -vlog01compat -work altera_ver {d:/office/fpga/quartus/quartus/eda/sim_lib/altera_primitives.v}

vlib verilog_libs/lpm_ver
vmap lpm_ver ./verilog_libs/lpm_ver
vlog -vlog01compat -work lpm_ver {d:/office/fpga/quartus/quartus/eda/sim_lib/220model.v}

vlib verilog_libs/sgate_ver
vmap sgate_ver ./verilog_libs/sgate_ver
vlog -vlog01compat -work sgate_ver {d:/office/fpga/quartus/quartus/eda/sim_lib/sgate.v}

vlib verilog_libs/altera_mf_ver
vmap altera_mf_ver ./verilog_libs/altera_mf_ver
vlog -vlog01compat -work altera_mf_ver {d:/office/fpga/quartus/quartus/eda/sim_lib/altera_mf.v}

vlib verilog_libs/altera_lnsim_ver
vmap altera_lnsim_ver ./verilog_libs/altera_lnsim_ver
vlog -sv -work altera_lnsim_ver {d:/office/fpga/quartus/quartus/eda/sim_lib/altera_lnsim.sv}

vlib verilog_libs/cycloneive_ver
vmap cycloneive_ver ./verilog_libs/cycloneive_ver
vlog -vlog01compat -work cycloneive_ver {d:/office/fpga/quartus/quartus/eda/sim_lib/cycloneive_atoms.v}

if {[file exists rtl_work]} {
	vdel -lib rtl_work -all
}
vlib rtl_work
vmap work rtl_work

vlog -vlog01compat -work work +incdir+D:/office/FPGA/SOC-Cortex-M/M0Test/Quartus/ip {D:/office/FPGA/SOC-Cortex-M/M0Test/Quartus/ip/xtal.v}
vlog -vlog01compat -work work +incdir+D:/office/FPGA/SOC-Cortex-M/M0Test/RTL/core {D:/office/FPGA/SOC-Cortex-M/M0Test/RTL/core/CORTEXM0INTEGRATION.v}
vlog -vlog01compat -work work +incdir+D:/office/FPGA/SOC-Cortex-M/M0Test/RTL/core {D:/office/FPGA/SOC-Cortex-M/M0Test/RTL/core/cortexm0ds_logic.v}
vlog -vlog01compat -work work +incdir+D:/office/FPGA/SOC-Cortex-M/M0Test/RTL/mcu {D:/office/FPGA/SOC-Cortex-M/M0Test/RTL/mcu/cmsdk_mcu_stclkctrl.v}
vlog -vlog01compat -work work +incdir+D:/office/FPGA/SOC-Cortex-M/M0Test/RTL/mcu {D:/office/FPGA/SOC-Cortex-M/M0Test/RTL/mcu/cmsdk_mcu_pin_mux.v}
vlog -vlog01compat -work work +incdir+D:/office/FPGA/SOC-Cortex-M/M0Test/RTL/mcu {D:/office/FPGA/SOC-Cortex-M/M0Test/RTL/mcu/cmsdk_ahb_cs_rom_table.v}
vlog -vlog01compat -work work +incdir+D:/office/FPGA/SOC-Cortex-M/M0Test/RTL/peripheral {D:/office/FPGA/SOC-Cortex-M/M0Test/RTL/peripheral/cmsdk_iop_gpio.v}
vlog -vlog01compat -work work +incdir+D:/office/FPGA/SOC-Cortex-M/M0Test/RTL/peripheral {D:/office/FPGA/SOC-Cortex-M/M0Test/RTL/peripheral/cmsdk_fpga_sram.v}
vlog -vlog01compat -work work +incdir+D:/office/FPGA/SOC-Cortex-M/M0Test/RTL/peripheral {D:/office/FPGA/SOC-Cortex-M/M0Test/RTL/peripheral/cmsdk_apb_watchdog_defs.v}
vlog -vlog01compat -work work +incdir+D:/office/FPGA/SOC-Cortex-M/M0Test/RTL/peripheral {D:/office/FPGA/SOC-Cortex-M/M0Test/RTL/peripheral/cmsdk_apb_uart.v}
vlog -vlog01compat -work work +incdir+D:/office/FPGA/SOC-Cortex-M/M0Test/RTL/peripheral {D:/office/FPGA/SOC-Cortex-M/M0Test/RTL/peripheral/cmsdk_apb_timer.v}
vlog -vlog01compat -work work +incdir+D:/office/FPGA/SOC-Cortex-M/M0Test/RTL/peripheral {D:/office/FPGA/SOC-Cortex-M/M0Test/RTL/peripheral/cmsdk_apb_subsystem.v}
vlog -vlog01compat -work work +incdir+D:/office/FPGA/SOC-Cortex-M/M0Test/RTL/peripheral {D:/office/FPGA/SOC-Cortex-M/M0Test/RTL/peripheral/cmsdk_apb_slave_mux.v}
vlog -vlog01compat -work work +incdir+D:/office/FPGA/SOC-Cortex-M/M0Test/RTL/peripheral {D:/office/FPGA/SOC-Cortex-M/M0Test/RTL/peripheral/cmsdk_apb_dualtimers_defs.v}
vlog -vlog01compat -work work +incdir+D:/office/FPGA/SOC-Cortex-M/M0Test/RTL/peripheral {D:/office/FPGA/SOC-Cortex-M/M0Test/RTL/peripheral/cmsdk_ahb_to_sram.v}
vlog -vlog01compat -work work +incdir+D:/office/FPGA/SOC-Cortex-M/M0Test/RTL/peripheral {D:/office/FPGA/SOC-Cortex-M/M0Test/RTL/peripheral/cmsdk_ahb_to_iop.v}
vlog -vlog01compat -work work +incdir+D:/office/FPGA/SOC-Cortex-M/M0Test/RTL/peripheral {D:/office/FPGA/SOC-Cortex-M/M0Test/RTL/peripheral/cmsdk_ahb_to_apb.v}
vlog -vlog01compat -work work +incdir+D:/office/FPGA/SOC-Cortex-M/M0Test/RTL/peripheral {D:/office/FPGA/SOC-Cortex-M/M0Test/RTL/peripheral/cmsdk_ahb_slave_mux.v}
vlog -vlog01compat -work work +incdir+D:/office/FPGA/SOC-Cortex-M/M0Test/RTL/peripheral {D:/office/FPGA/SOC-Cortex-M/M0Test/RTL/peripheral/cmsdk_ahb_gpio.v}
vlog -vlog01compat -work work +incdir+D:/office/FPGA/SOC-Cortex-M/M0Test/RTL/peripheral {D:/office/FPGA/SOC-Cortex-M/M0Test/RTL/peripheral/cmsdk_ahb_default_slave.v}
vlog -vlog01compat -work work +incdir+D:/office/FPGA/SOC-Cortex-M/M0Test/RTL {D:/office/FPGA/SOC-Cortex-M/M0Test/RTL/cortex_m0.v}
vlog -vlog01compat -work work +incdir+/office/fpga/soc-cortex-m/m0test/rtl/mcu {/office/fpga/soc-cortex-m/m0test/rtl/mcu/cmsdk_ahb_memory_models_defs.v}
vlog -vlog01compat -work work +incdir+D:/office/FPGA/SOC-Cortex-M/M0Test/Quartus/db/db {D:/office/FPGA/SOC-Cortex-M/M0Test/Quartus/db/db/xtal_altpll.v}
vlog -vlog01compat -work work +incdir+D:/office/FPGA/SOC-Cortex-M/M0Test/RTL/mcu {D:/office/FPGA/SOC-Cortex-M/M0Test/RTL/mcu/cmsdk_mcu_defs.v}
vlog -vlog01compat -work work +incdir+D:/office/FPGA/SOC-Cortex-M/M0Test/RTL/peripheral {D:/office/FPGA/SOC-Cortex-M/M0Test/RTL/peripheral/cmsdk_apb_watchdog_frc.v}
vlog -vlog01compat -work work +incdir+D:/office/FPGA/SOC-Cortex-M/M0Test/RTL/peripheral {D:/office/FPGA/SOC-Cortex-M/M0Test/RTL/peripheral/cmsdk_apb_watchdog.v}
vlog -vlog01compat -work work +incdir+D:/office/FPGA/SOC-Cortex-M/M0Test/RTL/peripheral {D:/office/FPGA/SOC-Cortex-M/M0Test/RTL/peripheral/cmsdk_apb_dualtimers_frc.v}
vlog -vlog01compat -work work +incdir+D:/office/FPGA/SOC-Cortex-M/M0Test/RTL/peripheral {D:/office/FPGA/SOC-Cortex-M/M0Test/RTL/peripheral/cmsdk_apb_dualtimers.v}
vlog -vlog01compat -work work +incdir+D:/office/FPGA/SOC-Cortex-M/M0Test/RTL/mcu {D:/office/FPGA/SOC-Cortex-M/M0Test/RTL/mcu/cmsdk_mcu_system.v}
vlog -vlog01compat -work work +incdir+D:/office/FPGA/SOC-Cortex-M/M0Test/RTL/mcu {D:/office/FPGA/SOC-Cortex-M/M0Test/RTL/mcu/cmsdk_mcu_sysctrl.v}
vlog -vlog01compat -work work +incdir+D:/office/FPGA/SOC-Cortex-M/M0Test/RTL/mcu {D:/office/FPGA/SOC-Cortex-M/M0Test/RTL/mcu/cmsdk_mcu_clkctrl.v}
vlog -vlog01compat -work work +incdir+D:/office/FPGA/SOC-Cortex-M/M0Test/RTL/mcu {D:/office/FPGA/SOC-Cortex-M/M0Test/RTL/mcu/cmsdk_mcu_addr_decode.v}
vlog -vlog01compat -work work +incdir+D:/office/FPGA/SOC-Cortex-M/M0Test/RTL/mcu {D:/office/FPGA/SOC-Cortex-M/M0Test/RTL/mcu/cmsdk_mcu.v}

vlog -vlog01compat -work work +incdir+D:/office/FPGA/SOC-Cortex-M/M0Test/Quartus/db/../../RTL {D:/office/FPGA/SOC-Cortex-M/M0Test/Quartus/db/../../RTL/tb_cm0.v}

vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc"  tb_cm0

add wave *
view structure
view signals
run -all
